1. Field of the Invention
The present invention relates to the design of a latch for storing data within a digital system. More specifically, the present invention relates to a method and an apparatus for latching data into a memory element in response to a clock signal.
1. Related Art
As the speed of computer systems continues to increase at an exponential rate, circuitry within the computer systems is coming under increasing pressure to operate at faster speeds. One problem in attaining higher speeds relates to the design of latches for storing data between computational operations.
FIG. 1 illustrates a conventional latching circuit that includes pass transistor 102, memory element 104 and driver 106. This latching circuit receives a data value on input 100 and stores the data value into memory element 104 when clock signal 101 makes pass transistor 102 transparent. This data value is subsequently driven by driver 106 onto output 108.
Memory element 104 is typically a bistable circuit or a capacitive storage element. Hence, input 100 must either overdrive the bistable circuit, or must charge up the capacitive storage element in order to change the value stored in memory element 104. However, in order to overdrive the bistable circuit or charge up the capacitive storage element, pass transistor 102 must drive a significant amount of current into memory element 104. Hence, pass transistor 102 must be sufficiently large to drive this current.
A sufficiently large pass transistor 102 has a large gate region, which creates a significant capacitive load for clock signal 101. Furthermore, note that clock signal 101 may have to drive a large number of latches. Hence, a significant load on each latch can significantly degrade the performance of clock signal 101, or may necessitate a very large driver.
Moreover, in order to keep pace with increasingly faster computer systems, it is desirable for the latch to operate at high speeds and to be able to drive a large amount of current.
What is needed is a method and an apparatus for latching a data value into a memory element in response to a clock signal, which places a minimal capacitive load on the clock signal, while operating at high speeds and driving a large amount of current.
One embodiment of the present invention provides a system for latching data in response to a clock signal. This system includes a memory element that is configured to store a data value. A latch input is coupled to the memory element, so that changes in the latch input change the data value stored in the memory element without waiting for an assertion of the clock signal. The system also includes a driver circuit that is configured to drive the data value stored in the memory element onto a latch output. The system additionally includes a clocking circuit that is configured to cause the driver circuit to drive the data value stored in memory element onto the latch output in response to an assertion of the clock signal.
In one embodiment of the present invention, the memory element includes a bistable circuit. In a variation on this embodiment, the memory element includes a keeper circuit comprising a first inverter and a second inverter. The first inverter and the second inverter are coupled together into a ring, so that the output of the first inverter is coupled to the input of the second inverter, and the output of the second inverter is coupled to the input of the first inverter.
In one embodiment of the present invention, the memory element includes a capacitive memory element.
In one embodiment of the present invention, the driver circuit includes a P-type transistor and an N-type transistor. The P-type transistor has a source coupled to VDD, a drain coupled to the latch output, and a gate coupled through the clocking circuit to a complement of the data value stored n the memory element. The N-type transistor has a source coupled to ground, a drain coupled to the latch output, and a gate coupled through the clocking circuit to the data value stored in the memory element.
In one embodiment of the present invention, the clocking circuit includes a first N-type pass transistor, with a drain coupled to the data value stored in the memory element, a source coupled through an inverter to a gate of a P-type transistor within the driver circuit, and a gate coupled to the clock signal. It also includes a second N-type pass transistor, with a drain coupled to a complement of the data value stored in the memory element, a source coupled to a gate of a N-type transistor within the driver circuit, and a gate coupled to the clock signal.
In one embodiment of the present invention, the clocking circuit includes a domino amplifier that is configured to drive the data value stored in the memory element into the driver circuit when the clock signal is asserted.
In one embodiment of the present invention, the clocking circuit includes an N-type clocking transistor coupled in series with drive transistors in the driver circuit. The gate of this N-type clocking transistor is coupled to the clock signal, so that asserting the clock signal causes the driver circuit to be activated.
In one embodiment of the present invention, the latch input is coupled to the input of a second latch. In this embodiment, the memory element is shared with the second latch and is located at the input of the second latch.
In one embodiment of the present invention, the system additionally includes a turnoff circuit that is configured to turn off the driver circuit after the data value stored in the memory element has been driven onto the latch output. In a variation on this embodiment, the turnoff circuit includes at least one P-type turnoff transistor with a source coupled to VDD, a drain coupled to a gate of a drive transistor within the driver circuit, and a gate coupled to a turnoff signal, so activating the turnoff signal causes the driver circuit to turn off. In a variation on this embodiment, the turnoff signal is derived from the latch input. In a variation on this embodiment, the turnoff signal is derived from the clock signal.